Company intelligence
AsFigo
Enabling semiconductor chip design and verification through open-source innovations!
About AsFigo
Chip Design and Verification start-up out of London, backed by decades of international semiconductor industry experience. We at AsFigo strongly believe that open source is the key to propelling the next generation of chip design engineers. For instance, worldwide workspace development requires access to tools and technologies at everyone's fingertips - without complicated licenses, NDAs, compute infrastructure etc. For many start-ups in the AI space, access to opensource tools and libraries mean a lot to keep their costs in check. We also develop solutions such as PySlint - an innovative testbench static checking tool that's the industry's first opensource SystemVerilog Testbench linter.
Verified activity
Signals from AsFigo
10 published signals
Research & Knowledge
AsFigo expects contributions from chip design verification using RustDV by the 2027 edition
Reported by Srinivasan Venkataramanan
Research & Knowledge
AsFigo observed that people often copy-paste LLM outputs into GitHub and then copy-paste them back, resulting in a waste of time.
Reported by Srinivasan Venkataramanan
Presence & Recognition
AsFigo announced that it is endorsing open source in chip design at the Open Road Initiative at DVCon India 2026.
Reported by Srinivasan Venkataramanan
Presence & Recognition
AsFigo participated in the Day 1 of the D.V.C. India 2026 conference on Open Source, where students demonstrated their work on open-source flow tools like Verilator, Yosys, and OpenLane.
Reported by AsFigo
Presence & Recognition
AsFigo participated in the day1 of the DVCon India 2026 event.
Reported by Srinivasan Venkataramanan
Presence & Recognition
AsFigo hosted the Open-Source Chip Design & Verification Bootcamp where Srinivasan Venkataramanan walked through Ben Cohen's RAG-SVA framework for AI-generated SystemVerilog Assertions.
Reported by Srinivasan Venkataramanan
Products & Services
AsFigo ported the CAN-Ethernet DUT + UVM TB to Verilator in under an hour with support from Ajeetha Kumari.
Reported by Srinivasan Venkataramanan
Presence & Recognition
AsFigo reserved a few more copies of Ben Cohen's Knowledge-driven AI with SVA-RAG for the panel at DVCon India 2026.
Reported by Srinivasan Venkataramanan
Presence & Recognition
AsFigo gave out few copies of Ben Cohen's Knowledge-driven AI with SVA-RAG at the Open Source event.
Reported by Srinivasan Venkataramanan
Presence & Recognition
AsFigo held a bootcamp keynote by Satish Sridharan Aura Semiconductor.
Reported by Srinivasan Venkataramanan