AsFigo participated in the Day 1 of the D.V.C. India 2026 conference on Open Source, where students demonstrated their work on open-source flow tools like Verilator, Yosys, and OpenLane.
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🎉 𝗙𝘂𝗹𝗹 𝗵𝗼𝘂𝘀𝗲 𝗮𝘁 𝗗𝗩𝗖𝗼𝗻 𝗜𝗻𝗱𝗶𝗮 𝟮𝟬𝟮𝟲. 🎉 Day 1's BOF on Open Source packed the room — overwhelmingly students. They're not waiting to be handed EDA…
Company
AsFigo
Enabling semiconductor chip design and verification through open-source innovations!
- Industry
- Computers and Electronics Manufacturing
- Location
- London, GB
- Company size
- 2–10 employees
About AsFigo
Chip Design and Verification start-up out of London, backed by decades of international semiconductor industry experience. We at AsFigo strongly believe that open source is the key to propelling the next generation of chip design engineers. For instance, worldwide workspace development requires access to tools and technologies at everyone's fingertips - without complicated licenses, NDAs, compute infrastructure etc. For many start-ups in the AI space, access to opensource tools and libraries mean a lot to keep their costs in check. We also develop solutions such as PySlint - an innovative testbench static checking tool that's the industry's first opensource SystemVerilog Testbench linter.
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Research & Knowledge
AsFigo expects contributions from chip design verification using RustDV by the 2027 edition
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AsFigo observed that people often copy-paste LLM outputs into GitHub and then copy-paste them back, resulting in a waste of time.
Presence & Recognition
AsFigo announced that it is endorsing open source in chip design at the Open Road Initiative at DVCon India 2026.
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